For Memory Expansion and Memory Pooling

CXL™ (Compute Express Link™) is an industry standard, open protocol for high speed and low latency communications between host accelerator, which are increasingly used in emerging applications, such as Artificial Intelligence (AI) and Machine Learning (ML).

SMART Modular, along with other industry leaders, such as Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Intel Corporation and Microsoft have teamed up to form an open industry standard group to develop technical specifications that facilitate breakthrough performance for emerging usage models while supporting an open ecosystem for data center accelerators and other high-speed enhancements. SMART calls its version of CXL, CMM-E3S.

CXL Protocols

The CXL standard defines 3 protocols that are dynamically multiplexed together before being transported via a standard PCIe 5.0 PHY at 32 GT/s:

• Native Widths: x16, x8, x4; x16 partitionable: x16, 2x8, 4x4, x8 + 2x4; x8 partitionable: x8, 2x4; degraded widths: x2, x1.

• Data Rate: 32 GT/s.

• Degraded support: 8 GT/s and 16 GT/s (128b/130b).

• Independent coherency models like CXL.cache, CXL.mem to support variety of use cases in Computational Storage, Network Acceleration and Persistent Memory.

• Plug and Play: either a PCIe or a CXL card/device can be plugged in.

• Reuse PCIe® PHY, channel, circuit, Retimer, etc.

CXL is Designed to Support Three Primary Device Types:

Example: Type-1 CXL Device

SMART NIC or video accelerators, which run specific algorithm function like video transcoding on data present in Host Memory.

Example: Type-2 CXL Device

FPGA or CPU based accelerators with integrated memory (like HBM or DDR).

Example: Type-3 CXL Device

Persistent Memory or Computational Storage devices sitting on CXL bus. Such devices cannot access Host Memory on their own.

CXL Memory Expansion

SMART Modular develops CXL Type 3 (CXL.mem) memory products to address the industry’s need for more memory per processor core. This approach allows for a more flexible and scalable memory architecture, where memory devices can be added or removed as needed, without the need to replace or upgrade the entire system.

Lower Total Cost of Ownership (TCO)

CMM-E3S is a more economical choice for expanding memory under current system architectures. Instead of purchasing 8 128GB DDR5 RDIMMs, clients can achieve equivalent memory capacity by employing 8 64GB DDR5 RDIMMs in conjunction with 8 CXL Add-In Cards (AICs). This configuration results in a remarkable reduction in costs, amounting to over 40%. SMART's upcoming CXL AIC is expected for launch in the near future.

CXL Memory Pooling

CXL 2.0 supports switching to enable memory pooling for efficient memory allocation. At 2.0 level, device can be partitioned as Multiple Logical Devices (MLD), allowing up to 16 hosts to simultaneously access different portions of the memory.

As an example, Host 1 (H1) can use half the memory in Device 1 (D1) and a quarter of the memory in D2 to finely match the memory requirements of its workload to the available capacity in the memory pool. The remaining capacity in D1 and D2 can be used by H2-H#.

• Available in EDSFF E3.S 2T (2U Short) Form Factor

• CXL-2.0 Compatible with PCIe Gen5 Speeds Running at 32GT/s

• Available in 64GB and 96GB Densities

• Supports Reliability, Availability and Serviceability (RAS) Features Added in CXL 2.0

• Powered by Only 12V Supply from EDSFF Compatible Edge Interface (SFF-TA-1009)

• Supports Sideband Interfaces for Real-Time Debug, Management and System Update, Enabling Out-of-Band Management of the Module

• Supports Additional Security Features to Protect Data from Side Channel Attacks