CXL™ is an industry standard, open protocol for high speed and low latency communications between host accelerator, which are increasingly used in emerging applications, such as Artificial Intelligence and Machine Learning.
SMART Modular, along with other industry leaders, such as Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Intel Corporation and Microsoft have teamed up to form an open industry standard group to develop technical specifications that facilitate breakthrough performance for emerging usage models while supporting an open ecosystem for data center accelerators and other high-speed enhancements.
- CXL™ leverages on PCIe® Gen5 Physical layer Infrastructure
- CXL uses a flexible processor port that can auto-negotiate to either the standard PCIe transaction protocol or the alternated CXL transaction protocols
- First generation CXL aligns to 32 Gbps PCIe Gen5
- Vendor agnostic CPU architecture, supported by multiple device manufacturers
CXL™ runs on PCIe Infrastructure
- Native Widths: x16, x8, x4
- x16 partitionable: x16, 2x8, 4x4, x8 + 2x4
- x8 partitionable: x8, 2x4
- Degraded widths: x2, x1
- Data Rate: 32GT/s
- Degraded support: 8GT/s and 16 GT/s (128b/130b)
- Independent coherency models like CXL.cache, CXL.mem to support variety of use cases in Computational Storage, Network Acceleration and Persistent Memory
- Plug and Play: Either a PCIe or a CXLTM card/device can be plugged in
- Reuse PCIe® PHY, channel, circuit, Retimer, etc.
SMART NIC or Video accelerators, which run specific algorithm function like video transcoding on data present in Host Memory.
FPGA or CPU based accelerators with integrated memory (like HBM or DDR).
Persistent Memory or Computational Storage devices sitting on CXL bus. Such devices cannot access Host memory on their own.
For more information on the CXL™ platform and SMART's developmental products, please contact us.