SMART offers DDR3 x64 SO-DIMMs with integrated ECC DRAMs. The conventional ECC approach has been to add an extra set of parity bits to validate the data being read from the DRAM array. This approach requires adding extra DRAMs which adds more data lines and cost. ECC software residing on the MPU or FPGA is also needed to detect and correct the error. With SMART’s SO-DIMM using integrated ECC DRAMs single bit errors are detected and corrected automatically. There is no need for additional DRAMs and no need for ECC software.
DDR3 SODIMM On-Chip ECC
Resources and Support
|File||Documentation||Document Size & Type||Last Updated|
|DRAM Product Line Brochure||3.2MB - PDF||4/4/2019|
|Sales Literature - DDR3 Module Product Overview||144KB - PDF||2/11/2020|
|Sales Literature - Industrial Grade DRAM Modules||226KB - PDF||2/11/2020|
|Data Sheet for PN SPT102ESV351816GC||GET DATASHEET||GET DATASHEET|