Memory Industry Terms and Acronyms

Term	Definition
3D-DRAM	A Mitsubishi device based on the CDRAM (qv) that has multiple banks and static columns along with a second serial port. It is specifically designed to be a 3D video frame buffer.
Access Time	The time to access information stored in a memory device or module. Measured in nanoseconds (ns).
Adaptable Memory Socket	The adaptable memory socket (AMS) concept by SMART Modular Technologies describes synchronous DRAM (SDRAM) modules, fast page mode (FPM) and extended data out (EDO) modules that operate interchangeably in the same socket in a system designed to work with any of the three.
Address Depth	Number of address locations per I/O pin of a module or in a memory component. (e.g. 1Mx4 memory device has an address depth of 1M = 1024K = 1048576 address locations for each of 4 I/O pins).
AMS	See: "Adaptable Memory Socket".
Application Specific Memory ICs	Memory ICs that are intended for specific applications. These are not intended for main memory and/or not manufactured to an open standard.
Aramid	High reliability substrate material used instead of FR-4.
Asynchronous	Not synchronized with the system clock.
Asynchronous DRAM	FPM DRAM and EDO DRAM (qv). These architectures are still in production but are being replaced by advanced designs.
ATA	AT Attachment standard. The mobile equivalent of the IDE standard. Standard for hard disk drives for the IBM AT computer bus. Widely used for hand held computers and portable equipment including cameras. Allows any ATA interfaced product to work with any host using ATA protocol without requiring changes to software. Is forward and backward compatible.
Attribute Memory	PC Cards are supposed to contain CIS (Card Information Structure). This informs the machine, when interrogating the card during the first insertion, what kind of card it is and how it is structured and configured (the attributes of the card). This information can reside at a particular address in the Flash device itself or in a special separate device within the card. When this piece of soft information (CIS) resides in the Flash, it is referred to as residing in the Common Memory ("Common" since that's what the user uses for his/her data). When it resides in a separate device, that device is referred to as Attribute Memory. Attribute Memory is normally some form of ROM - either a MROM or EEPROM.
Bandwidth (Component)	The number of bits transferred per second per pin by a DRAM component. This is usually stated in Megabits or Gigabits per second per pin (Mb/s/p or Gb/s/p).
Bandwidth (System)	The number of bytes transferred in a second between the system memory bus and a DRAM bank of main memory (not just a single DRAM component). The most common main memory bus in computers today transfers 8 bytes (64 bits) at a time. Even if the system uses 72 bits, 8 bits are for ECC and the data transferred is still 8 bytes at a time. This is usually stated in Megabytes or Gigabytes per second (MB/s or GB/s).
Bill of Materials	List of all the things required to manufacture, package and ship a module.
Bit	The smallest unit used by a computer. A bit may have a value of 1 or 0 like a simple light switch that can be either on or off.
Block Erase	Refers to erasing a block of cells at one time.
Buffered Modules	Modules that have additional ICs that buffer the DRAMs from the signals supplied by the system.
Bulk Erase	Refers to erasing all cells of the device at one time.
Burst	A higher-speed method of fetching a cache line over a slow bus. In normal bus transactions, one address output is required for every read cycle. In a bursting bus protocol, one address is output, and several pieces of read data are expected in return.
Burst Mode	Type of burst access. Burst mode can be linear or interleaved depending on the processor.
Bus Width	The number of data bits you can input or access simultaneously. Common bus widths of DRAM modules are 32, 36, 40, 64, 72, 80 bits.
Byte	A byte is 8 bits (taken together). Computer memory capacities are commonly measured in multiples of Megabytes.
Cache	A high-speed memory array which acts as a buffer between the CPU and main memory, cache consists of a controller, directory and data memory.
Cache Hit	A cache hit occurs when the data which the CPU want is located in cache.
Cache Miss	A cache miss occurs when the data which the CPU wants is not located in cache and must be fetched from main memory.
CAS	Column Address Strobe. Signal that selects the column to be accessed in a DRAM.
CAS Latency	Defines the number of clock cycles after which the data is available on bus once CAS has been asserted.
CDRAM	CacheDRAM. A Mitsubishi device with a single bank and an internal static column; used as a buffer memory in hard drives and as a texture memory for game displays.
CFI	Common flash interface intended to make the flash erase/programming algorithm transparent to the user. Intel, AMD and others have been working on this for a long time. It may take another year or more to complete the standard.
CIS	Card Information Structure. The CIS is a read-only register that indicates the attribute information of functions in the ATA Card.
Clock Speed	Frequency of the clock in MHz.
COASt	Acronym coined by Intel referring to L2 Cache meaning Cache On A Stick (COASt).
Common Flash Interface (CFI)	Common flash interface intended to make the flash erase/programming algorithm transparent to the user. Intel, AMD and others have been working on this for a long time. It may take another year or more to complete the standard.
CompactFlash Card	Introduced by Sandisk in 1994. One fourth the size of a PC card. 36 mm long, 43 mm wide and 3.3 mm thick. ATA interface. Uses 50 pins. Takes a passive adapter to use it in a PC card slot.
Component	Any passive items (resistors, capacitors, etc.), or active ICs (DRAMs, registers, buffers, etc.) used to make a module.
Concurrent RDRAM	A DRAM fabricated with a proprietary bus architecture that requires a Rambus license. Currently in use for game graphics. See "RDRAM".
Configuration	See "Organization".
Custom Design	Customer specific modules not in accordance with industry standards.
Cycle Time	Period of the clock in ns. (Equals reciprocal of the clock frequency.)
Data Width	Total number of bits/bytes of data that can be accessed (read or written) simultaneously.
DDR SDRAM	Double Data Rate SDRAM. Formerly termed "SDRAM II".
Defect Management	An on board controller implements defect management algorithms by keeping track of bad sectors and working around them, remapping the available good sectors (blocks). The controller keeps an updated map of good sectors and uses the available good memory cells. This is completely transparent to the user.
Defect Management	An on board controller implements defect management algorithms by keeping track of bad sectors and working around them, remapping the available good sectors (blocks). The controller keeps an updated map of good sectors and uses the available good memory cells. This is completely transparent to the user.
Density	Total capacity of memory ICs (in kilobits or megabits), or total capacity of memory modules (in kilobytes or megabytes).
Depth	See "Address Depth".
Device Features	Specific characteristics of the devices used to build a modules.
DIMM	Dual In-Line Memory Module (DIMM). Electrical contacts are in 2 straight lines on each side of the modules.
Direct RDRAM	The next generation of Rambus SDRAM technology that is expected to double the bandwidth of the present "concurrent" RDRAM.
Dirty Bit	Used only in copy-back caches, this bit identifies a location which has been modified (by the CPU) within the cache, and has yet to be updated in main memory.
DQM	Data Input/Output Mask. A signal that is used to mask data from being accessed from or written into memory.
DRAM	Dynamic Random Access Memory (DRAM). A memory IC that must have power on and must also be refreshed periodically to maintain correct data (Dynamic). Data stored in the memory can be randomly controlled by RAS/CAS signals (Random Access). All DRAMs have multiplexed addressing.
DRAM Modules	Modules built using DRAMs.
DRAM-like Flash	A type of Flash memory component that reads like a DRAM (with clocks and multiplexed addresses), and writes like a standard Flash IC.
DRAM-like Flash Module	Modules made with DRAM-like Flash components having DRAM module pinouts so they can be used in standard DRAM sockets.
Dual Voltage Flash	Flash that uses two separate power supplies. One for programming and erasing and a separate (usually a lower voltage) one for reading.
ECC	Error Checking and Correction. A method of detecting and correcting system memory errors by adding additional bits and using a special algorithm.
EDO DRAM	Extended Data Out DRAM. A DRAM that holds the data on the system memory bus until the beginning of the next cycle. Named to distinguish it from FPM DRAM which removes the data from the memory bus before the completion of the cycle.
Endurance	The number of times a flash chip can be reprogrammed. Minimum is one hundred cycles and many devices exceed a minimum of one million cycles.
Error Detection	Some memory designs allow the system to detect errors and correct during system operation. See "Parity" and "ECC".
ESDRAM	Enhanced SDRAM from Enhanced Memory Systems, Inc.
Extended Data Out	See "EDO DRAM".
Fast Page Mode	See "FPM".
Flash File System (FFS)	Software working with the operating system to interface with linear PC cards.
Flash File System (FFS)	Software working with the operating system to interface with linear PC cards.
Flash Memory Devices	Non-volatile semiconductor ICs. They are derivatives of EPROM an EEPROM technologies. The architecture of flash chips is based on the idea that it will be seldom written to but will be read often. Rapidly replacing the other non-volatile memory types (ROM, EPROM & EEPROM) in many applications.
Flash Programming Voltage	The voltage applied to a special (VPP) pin needed to write to (program) a Flash device or Flash module.
Flash RAM	See "DRAM-like Flash".
Flash Transition Layer (FTL)	Software working with the operating system to interface to Miniature cards.
Flow-through	An SRAM device in which the data outputs are not registered and hence are driven onto the bus one clock cycle after the access has been initiated. Allows a faster access to the data. See also "Pipelined".
FPM	Fast Page Mode. The standard operating mode of DRAMs until the introductions of EDO and SDRAM. During the read cycle, output data is switched off of the data bus when the column address strobe (CAS) switches high in the cycle. This is now the slowest operating mode of DRAMs.
FPM DRAM	Fast Page Mode DRAM. A DRAM that enables a stream of data (a page) to be either read or written by cycling the Column Address Strobe. Originally DRAMs only transferred one bit of data each cycle and could not stream the data.
FR-4	Common glass epoxy substrate material used for memory modules.
Gigabit (Gb)	1K Megabits, 1024 times 1,048,576 bits. 1 Gigabit is 1,073,741,824 bits.
Gigabytes (GB)	1K Megabytes, 1024 times 1,048,576 bytes. 1 Gigabytes is 1,073,741,824 bytes.
Gold Lead Finish	A term used for gold plated electrical contacts (pins) on memory modules.
Height	Specifies the total height of a module.
IDE	Integrated Device Electronics. The industry storage interface standard for hard disk drives. It allows any IDE flash card to work on any system using IDE protocol without changing the software. It is forward and backward compatible.
Interleave	The process of retrieving data alternatively from two or more memory pages (of the same SRAM), or from two or more devices (on a module or card)
JEDEC	Joint Electronic Device Engineering Council. This organization develops industry standards for electronic devices, including memory modules.
JEIDA	Japanese Electronics Industry Development Association.
Kilobit (Kb)	1K bits, where K is the binary number 1024 (210), a Kilobit is 1024 bits.
Kilobyte (KB)	1K bytes, where K is the binary number 1024 (210), a Kilobyte is 1024 bytes.
L2 Cache	Alternative nomenclature for Level 2 (secondary) cache.
Latency	The time it takes to address an array location inside the chip and get data to the chip's I/O.
Lead Finish	The type of metal used on the pins or electrical contacts on memory modules. See solder lead finish, or gold lead finish.
Length	Specifies the total length of a module.
Linear Flash	Linear flash cards will work only on computers that have the same flash filing system (from the same FFS vendor with the same revision). Interoperability is limited.
Linear Interface	Uses a flash file management software system called the Flash File System to interface with PC Cards. Uses a flash management system called the Flash Transition Layer (FTL) to interface with Miniature Cards. This software is on the host and must work with the operating system. Linear cards may have a PCMCIA standard interface hardware and firmware on the card or can be populated with just flash chips.
Low Profile	A term used to indicate that the height of a module is less than a standard height.
Match Tag	A particular tag SRAM device used on L2 Cache Modules which generates a "Match" output by comparing the tag data stored in the tag SRAM with the address being requested. An active-high Match tag will generate a "1" in case of cache-hit and "0" in case of cache-miss.
MDRAM	Multibank DRAM. A MoSys device with several internal banks, each with its own static column buffer. The MDRAM has the capability of moving data between static columns without external interference. It is designed for graphics applications.
MediaStik	Introduced by Nexcom June 1997. It is 45 mm long 15 mm wide. Serial interface using 8 contacts similar to those used in smart cards. It has an ATA/IDE controller on board.
Mega Storage Device	A line of cards Introduced by Panasonic in September 1997. They are 42.6 mm long, 45 mm wide and either 3.3 mm or 5 mm thick depending on whether it is intended of a type I or type II PC card slot. Can have either a linear or an ATA interface. Uses 68 pins. Needs no adapter because it fits PC card slots.
Megabits (Mb)	1K Kilobits, 1024 times 1024 bits. 1 Megabit is 1,048,576 bits.
Megabytes (MB)	1K Kilobytes, 1024 times 1024 bytes. 1 Megabyte is 1,048,576 bytes.
Memory Stick	Not yet introduced. Sony, Casio, Fujitsu, Olympus, Sanyo and Sharp are working on it. It is 50 mm long, 21 mm wide and 2.8 mm thick. Has a synchronous bi-directional serial interface. Uses 10 pins.
Miniature Card	Launched by Intel January 1996. It is 33 mm long, 38 mm wide and 3.5 mm thick. Is linear and requires Flash Transition Layer software in the host. Uses 40 pins. Requires a passive adapter card to work in a PC card slot.
Module Speed	The access time and/or operating frequency of a module.
Multi-Level Cell	Flash technology that allows a cell to hold 2 bits of data instead of just one. (May be extended to 4 bits per cell in the future.)
MultiMedia Card (MMC)	Introduced by Siemens and Sandisk December 1997. It is 32 mm long, 24 mm wide and 1.4 mm thick. Is about the size of a quarter (coin). Uses a 7 pin serial interface.
Nand Flash Device	Flash architecture designed to interface like a magnetic hard disk drive. Uses Fowler-Nordheim Tunneling (FNT) for both erasing and programming. Does not have random access. Currently available in higher density than NOR flash.
Nanosecond	One billionth of a second.
Nonvolatile	Nonvolatile memory components and memory modules do not lose data stored in them when the power is turned off. e.g. Flash.
Nor Flash Device	Initially designed to replace EPROM devices for code storage. Designed for random access. Erased by Fowler-Nordheim Tunneling (FNT). Programmed by Hot Electron Injection (HEI). Uses a floating gate cell structure and one transistor per cell.
Operating Mode	See "FPM", "EDO", "SDRAM", "Asynchronous" and "Synchronous".
Organization	The address depth and bus width of a memory component, or a memory module. Component example: 16Meg DRAMs: 1Mx16, 2Mx8 or 4Mx4. Module example: 168-pin modules: can be 1/2/4Mx64 or 1/2/4Mx72.
Package Type	The type of package of a memory component. See SOJ, TSOP and TQFP. (Typically, plastic material is used for memory devices which are used on memory modules.)
Page	One page represents the number of bits in a DRAM that can be accessed from one row address. The page size depends on the number of column addresses. A device with 10 column address pins has 1,024 bits.
Parallel Presence Detect	The original presence detect scheme. The density and speed were indicated by a binary code (logical ones and zeroes). This code was implemented on parallel pins of the module by placing resistors tied to ground (a logical zero) or not having a resistor (a logical one) connected to each of the pins. The computer would detect the presence of the module, the density of the module and the speed of the module via this parallel code. This allowed the amount of memory and speed of the memory to be known as well as the ability to tell if incorrect modules had been installed. This was used on 30 and 72 pin SIMMs. Parallel presence detect uses several pins in parallel to detect the module.
Parity	A method of detecting data errors by adding one additional bit (a parity bit) to each byte. See also "Parity Bit".
Parity Bit	Parity can be even or odd. If a bit pattern has an odd number of bits in an even parity machine, the parity bit will be "turned on" (set to one) and vice versa. This method is used to permit internal checking in data transfer. See also "Parity".
PC Flash Card	Formerly called a PCMCIA card. Full size flash card, 85.6 mm long, 54 mm wide and 3.3 mm, 5 mm or 10 mm thick for type I, type II and type III form factors respectively. Can be linear, ATA or IDE. Uses 68 pins.
PC SDRAM	Synchronous DRAM (SDRAM) (qv) conforming to a tight set of timing parameters specified by Intel for a 100MHz memory bus. See the section titled PC SDRAM, The Interim Solution for a detailed description.
PCB	Printed Circuit Board, sometimes called PWB (Printed Wiring Board). The substrate of a memory module that holds the memory components. See FR-4 or Aramid.
PCMCIA	Acronym for Personal Computer Memory Card International Association. This is the organization setting the standards for PC Cards.
Pinout	Term used to describe the signal and power assignment of each pin of a module or memory component.
Pins	Contacts on a memory module even though most memory modules have edge connector contacts, these are called pins.
Pipeline	A method for increasing DRAM and SRAM performance by allowing data output while new data is accessed.
Power	Voltage multiplied by current. An electrical specification of a module. Another term for the voltage applied as in "power and ground pins".
Presence Detect	See: "Parallel Presence Detect" and "Serial Presence Detect".
Profile	A term applied to the dimensions of a module especially height and thickness, (low, thin, etc.).
Programming Voltage	See "Flash Programming Voltage".
QUADCAS	A type of DRAM that implements 4 each x1 DRAMs, each with a separate CAS signal, (4 separate CAS signals are called quadCAS) in a single package. This replaces 4 separate 1Mx1 or 4Mx1 DRAM components with a single package for parity bits on a module.
Rambus DRAM	See "RDRAM"
RAS	Row Address Strobe. Signal that selects the row to be accessed in a DRAM.
RDRAM	(Rambus DRAM) A dynamic RAM chip from Rambus, Inc. It transfers data at 500MBytes/sec (3-10 times faster than DRAM and VRAM chips), eliminating the need for memory caches. It requires modified motherboards.
Refresh	DRAMs are made up of cells that must be recharged periodically to prevent loss of data. The refresh process restores the charge to these cells.
Refresh Rate	DRAM cells are arranged in rows, and the cells in each row are refreshed simultaneously. The refresh rate refers to the number of rows that must be refreshed. Refresh rates can be 1K, 2K, 4K and 8K. Also see "Refresh"
Registered Modules	A DRAM Memory module that has registers (buffers) on board. This allows system drivers to experience a single load per module. Without these registers (buffers), the system drivers experience the collective loading of multiple DRAMs on the module.
SDRAM	Synchronous Dynamic Random Access Memory. Intended for main memory and/or manufactured to an open standard. Delivers bursts of data at very high speeds using a synchronous (synchronized with the system clock) interface. Currently, bus speeds up to 100 MHz are supported by SDRAM. See also "Synchronous" and "DRAM".
Sector Erase	Refers to erasing a sector (a group) of cells at one time. Usually applied to flash which is to be used in place of a floppy or hard drive.
Self-Refresh	A refresh mode that provides the DRAM with the ability to refresh itself while in an extended standby mode (sleep or suspended). See "Refresh Rate".
Serial Presence Detect	The combinations of density, speed, mode of operation (FPM or EDO) required too many pins and too much complexity added to the system to continue to use the parallel presence detect system. Serial presence detect replaced the parallel methodology and was standardized by JEDEC (at the request of major system manufacturers). A serial EEPROM is used to store the presence detect information as well as much more information. This information is read from the module serially (Hence the name). Many bytes of information can stored such as where, when, who made the module. Some of the technical details about the module can be stored. Modules can have serial numbers. The details are available in the JEDEC standard. Serial presence detect uses 2 pins (one for data and one for "enable") to detect the presence of modules serially.
SGRAM	Synchronous Graphics RAM - an SDRAM with special features directly applicable to graphics applications. Open standards have been established and further standards work for higher densities continues.
SIMM	Single In-line Memory Module. Electrical contacts are in a single line with opposing pins on either side of a module tied together to form one electrical contact.
Single Voltage Flash	Flash that uses a single voltage for programming/erasing and reading. Usually uses on chip charge pumps to generate the programming/erase voltage internally. Referred to as 5-volt only, 3-volt only etc. flash.
SIP	Single In-line Package. Term used for modules that have a single row of pins on them (instead of contacts for edge connectors).
SLDRAM	Formerly termed "SyncLink DRAM." Using a revolutionary bus interface, SLDRAM offers an approach similar to Direct RDRAM, but is being standardized in JEDEC as an open standard.
Small Form Factor Flash Cards (SFFFC)	Flash cards with a size significantly smaller that of PC flash cards.
SMT	Surface Mount Technology. Manufacturing technology for mounting electronic components directly into the surface of PCB boards.
SO DIMM	Small Outline Dual In-line Memory Module. Small form factor DIMM, designed for notebook and handheld computers.
SOJ Package	Small Outline J-lead Package. A surface mount IC package with the leads bent down and under the body of the package.
Solid State Floppy Disk Card (SSFDC) or Smart Media Card	Introduced by Toshiba in November 1995. Samsung purchased a license to build and market this in June 1996. It is 45 mm long, 37 mm wide and 0.76 mm thick. The thinnest card on the market. Holds a single flash chip. Uses ATA interface when inserted into an active (has an ATA controller on it) adapter.
Speed	See "Module Speed".
SRAM	Static Random Access Memory. Can be asynchronous, synchronous, pipelined burst mode or flow-through. Static RAMs need no refresh, but are volatile.
Substrate	See "Aramid" or "FR-4". Basic PCB that modules are made with.
Synchronous	A memory component that is designed to be synchronized with the system clock
Tag Bits	Contents of a Tag RAM. See also "Tag RAM".
Tag RAM	Cache-tag. The memory used to store the address tags of corresponding lines currently held in the cache data RAM and then compares the stored tags to the current address to determine a cache hit or miss.
Technology Independence	Value-added feature from SMART Modular Technologies indicating its unbiased independence in the selection of technologies best suited to the design and development of specific embedded computer modules, memory modules or memory cards for any customer
Thickness	Indicates the total thickness of a module including PCB board and ICs. It depends largely on the packaging type of the ICs (SOJ, TSOP, TQFP) and whether parts are mounted on one side or both sides of the PCB.
Time-to-Market	System-development parameter minimized by SMART Modular Technologies' competence in the design, test, and manufacture of memory modules, memory cards and embedded single board computers
TQFP	Thin Quad Flat-Pack Package. Thin plastic packages with leads on all 4 sides. Usually used with high pin count packages such as the 100-pin TQFP for 32Kx32 SRAMs.
TSOP Package	Thin Small Outline Package. A surface mount IC package that is thinner than the SOJ package and has the leads bent down and outward. When viewed from one end of the package, the leads have the shape of seagull wings when the bird is in flight.
Unbuffered Modules	Memory modules that have no on-board buffers.
VCC	Term used for the power supply on logic ICs. Memory ICs use VDD and VCC interchangeably.
VCM	Virtual Channel Memory. NEC is proposing an open standard on an SDRAM that the firm describes as a Virtual Channel Memory. See the discussion in the previous section
VDD	Term used for the power supply pin on DRAMs and DRAM modules.
Volatile	Volatile memory components and memory modules lose data when power is turned off.
VPP	The voltage used for flash programming and erase functions. It gets its name from the name of the pin on the chip package that the programming and erase voltage was connected to.
Wear Leveling	Use of an algorithm to maximize the endurance of a flash card. All flash devices in a card are programmed with equal frequency. This prevents any one flash component from being programmed to its endurance limit while other flash components on the same card may experience little or no programming.
Width	See "Bus Width and Module Width".
Write Protect	Just as floppy disk data is protected from accidental and/or intentional alteration by write protecting it, so is the data in a PC Card. The way it is achieved, however, is slightly different. There is a switch on the rear edge of the card which has two positions - Write Protected and Write Enabled. In the former position the card is protected from inadvertent writes and erases. In the latter position the card can be written to and erased.
ZIP	Zig-Zag In-line Package. When used for a memory module, it means two rows of pins which are in line. If a line is drawn from pin to pin, it will be a zig zag line back and forth from row to row.

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